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ltc4267 1 4267fc power over ethernet ieee 802.3af pd interface with integrated switching regulator the ltc ? 4267 combines an ieee 802.3af compliant pow- ered device (pd) interface with a current mode switching regulator, providing a complete power solution for pd applications. the ltc4267 integrates the 25k signature resistor, classi? cation current source, thermal overload pro- tection, signature disable and power good signal along with an undervoltage lockout optimized for use with the ieee- required diode bridge. the precision dual level input current limit allows the ltc4267 to charge large load capacitors and interface with legacy poe systems. the current mode switching regulator is designed for driving a 6v rated n-channel mosfet and features pro- grammable slope compensation, soft-start, and constant frequency operation, minimizing noise even with light loads. the ltc4267 includes an onboard error ampli? er and voltage reference allowing use in both isolated and nonisolated con? gurations. the ltc4267 is available in space saving, low pro? le 16-pin ssop or dfn packages. ip phone power management wireless access points security cameras power over ethernet complete power interface port for ieee 802 ? .3af powered device (pd) onboard 100v, 400ma uvlo switch precision dual level inrush current limit integrated current mode switching regulator onboard 25k signature resistor with disable programmable classi? cation current (class 0-4) thermal overload protection power good signal integrated error ampli? er and voltage reference low pro? le 16-pin ssop and 3mm 5mm dfn packages features descriptio u applicatio s u typical applicatio u class 2 pd with 3.3v isolated power supply p vcc pwrgd ngate sense i th /run v fb pgnd p out v portp r class sigdisa v portn ltc4267 + + r class 68.1 ? 1% 5f min 10k 470 100k 60.4k p vcc p vcc 4.7f 320f min 22nf pa1133 ps2911 bas516 tlv431 sbm1040 smaj58a 3.3v 1.5a chassis hd01 + ? + ? hd01 ?48v from data pair ?48v from spare pair 4267 ta01 si3440 0.1 ? 6.8 k 10 k 0.1f , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc4267 2 4267fc v portn with respect to v portp voltage ... 0.3v to C 100v p out , sigdisa, ? p ? w ? r ? g ? d voltage ..................... v portn + 100v to v portn C 0.3v p vcc to pgnd voltage (note 2) low impedance source ........................... C 0.3v to 8v current fed .......................................... 5ma into p vcc r class voltage .................v portn + 7v to v portn C 0.3v ? p ? w ? r ? g ? d current .....................................................10ma r class current .....................................................100ma ngate to pgnd voltage ...........................C 0.3v to p vcc v fb , i th /run to pgnd voltages ................ C 0.3v to 3.5v order part number dfn part* marking consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grades are identi? ed by a label on the shipping container. 4267 4267 ltc4267cdhc ltc4267idhc (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v portn supply voltage voltage with respect to v portp pin maximum operating voltage (notes 4, 5, 6) C 57 v signature range C 1.5 C 9.5 v classi? cation range C 12.5 C 21 v uvlo turn-on voltage C 34.8 C 36.0 C 37.2 v uvlo turn-off voltage C 29.3 C 30.5 C 31.5 v v turnon p vcc turn-on voltage voltage with respect to pgnd 7.8 8.7 9.2 v v turnoff p vcc turn-off voltage voltage with respect to pgnd 4.6 5.7 6.8 v v hyst p vcc hysteresis v turnon C v turnoff 1.5 3.0 v v clamp1ma p vcc shunt regulator voltage i pvcc = 1ma, v ith /run = 0v, voltage 8.3 9.4 10.3 v with respect to pgnd sense to pgnd voltage .............................. C 0.3v to 1v ngate peak output current (<10s) ..........................1a operating ambient temperature range ltc4267c ................................................ 0c to 70c ltc4267i .............................................C 40c to 85c junction temperature gn package ...................................................... 150c dhc package .................................................... 125c storage temperature range ...................C 65c to 150c lead temperature (soldering, 10 sec) .................. 300c order part number gn part marking 4267 4267i ltc4267cgn ltc4267ign t jmax = 125c, ja = 43.5c/w exposed pad (pin 17) must be soldered to electrically isolated pcb heat sink t jmax = 150c, ja = 90c/w 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 top view dhc16 package 16-lead (3mm 5mm) plastic dfn i th /run pgnd ngate p vcc r class nc v portn nc v fb pgnd sense v portp sigdis a pwrgd p out nc top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pgnd i th /run ngate p vcc r class nc v portn pgnd pgnd v fb sense v portp sigdisa pwrgd p out pgnd order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ absolute axi u rati gs w ww u for atio package/order i uu w electrical characteristics
ltc4267 3 4267fc the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v margin v clamp1ma C v turnon margin 0.05 0.6 v i vportn_on v portn supply current when on v portn = C 48v, p out , ? p ? w ? r ? g ? d, sigdisa floating 3 ma i pvcc_on p vcc supply current (note 7) normal operation v ith /run C pgnd = 1.3v 240 350 a start-up p vcc C pgnd = v turnon C 100mv 40 90 a i vportn_class v portn supply current v portn = C17.5v, p out tied to v portp , r class , 0.35 0.5 0.65 ma during classi? cation sigdisa floating (note 8) ?i class current accuracy 10ma < i class < 40ma, C12.5v v portn C 21v 3.5 % during classi? cation (notes 9, 10) r signature signature resistance C1.5v v portn C 9.5v, p out tied to v portp , 23.25 26.00 k ieee 802.3af 2-point measurement (notes 4, 5) r invalid invalid signature resistance C1.5v v portn C 9.5v, sigdisa and p out tied to 9 11.8 k v portp , ieee 802.3af 2-point measurement (notes 4, 5) v ih signature disable with respect to v portn 3 57 v high level input voltage high level invalidates signature (note 11) v il signature disable with respect to v portn 0.45 v low level input voltage low level enables signature r input signature disable, input resistance with respect to v portn 100 k v pg_out power good output low voltage i = 1ma v portn = C 48v, 0.5 v ? p ? w ? r ? g ? d referenced to v portn power good trip point v portn = C 48v, voltage between v portn and p out (note 10) v pg _fall p out falling 1.3 1.5 1.7 v v pg_rise p out rising 2.7 3.0 3.3 v i pg_leak power good leakage current v portn = 0v, ? p ? w ? r ? g ? d fet off, v ? p ? w ? r ? g ? d = 57v 1 a r on on-resistance i = 300ma, v portn = C 48v, measured from 1.0 1.6 v portn to p out (note 10) 2 v ithshdn shutdown threshold (at i th /run) p vcc C pgnd = v turnon + 100mv 0.15 0.28 0.45 v i thstart start-up current source at i th /run v ith /run C pgnd = 0v, p vcc C p gnd = 8v 0.2 0.3 0.4 a v fb regulated feedback voltage referenced to pgnd, p vcc C p gnd = 8v (note 12) 0.780 0.800 0.812 v i fb v fb input current p vcc C p gnd = 8v (note 12) 10 50 na g m error ampli? er transconductance i th /run pin load = 5a (note 12) 200 333 500 a/v ?v o(line) output voltage line regulation v turnoff < p vcc < v clamp (note 12) 0.05 mv/v ?v o(load) output voltage load regulation i th /run sinking 5a, p vcc C p gnd = 8v (note 12) 3 mv/a i th /run sourcing 5a, p vcc C p gnd = 8v (note 12) 3 mv/a i pout_leak p out leakage v portn = 0v, power mosfet off, 150 a p out = 57v (note 13) i lim_hi input current limit, high level v portn = C 48v, p out = C 43v (note 14, 15) 0c t a 70c 325 375 400 ma C 40c t a 85c 300 375 400 ma i lim_lo input current limit, low level v portn = C48v, p out = C43v (note 14, 15) 80 140 180 ma f osc oscillator frequency v ith /run C pgnd = 1.3v, p vcc C p gnd = 8v 180 200 240 khz dc on(min) minimum switch on duty cycle v ith /run C pgnd = 1.3v, v fb C pgnd = 0.8v, 6 8 % p vcc C p gnd = 8v dc on(max) maximum switch on duty cycle v ith /run C pgnd = 1.3v, v fb C pgnd = 0.8v, 70 80 90 % p vcc C p gnd = 8v electrical characteristics
ltc4267 4 4267fc the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units t rise ngate drive rise time c load = 3000pf, p vcc C p gnd = 8v 40 ns t fall ngate drive fall time c load = 3000pf, p vcc C p gnd = 8v 40 ns v imax peak current sense voltage r sl = 0, p vcc C p gnd = 8v (note 16) 90 100 115 mv i slmax peak slope compensation output current p vcc C p gnd = 8v (note 17) 5 a t sfst soft-start time p vcc C p gnd = 8v 1.4 ms t shutdown thermal shutdown trip temperature (notes 14, 18) 140 c note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: p vcc internal clamp circuit self regulates to 9.4v with respect to pgnd. note 3: the ltc4267 operates with a negative supply voltage in the range of C 1.5v to C 57v. to avoid confusion, voltages for the pd interface are always referred to in terms of absolute magnitude. terms such as maximum negative voltage refer to the largest negative voltage and a rising negative voltage refers to a voltage that is becoming more negative. note 4: the ltc4267 is designed to work with two polarity protection diode drops between the pse and pd. parameter ranges speci? ed in the electrical characteristics section are with respect to this product pins and are designed to meet ieee 802.3af speci? cations when these diode drops are included. see the application information section. note 5: signature resistance is measured via the two-point v/ i method as de? ned by ieee 802.3af. the pd signature resistance is offset from the 25k to account for diode resistance. with two series diodes, the total pd resistance will be between 23.75k and 26.25k and meet ieee 802.3af speci? cations. the minimum probe voltages measured at the ltc4267 pins are C 1.5v and C 2.5v. the maximum probe voltages are C 8.5v and C 9.5v. note 6: the pd interface includes hysteresis in the uvlo voltages to preclude any start-up oscillation. per ieee 802.3af requirements, the pd will power up from a voltage source with 20 series resistance on the ? rst trial. note 7: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 8: i vportn_class does not include classi? cation current programmed at the r class pin. total current in classi? cation mode will be i vportn_class + i class (see note 9). note 9: i class is the measured current ? owing through r class . i class accuracy is with respect to the ideal current de? ned as i class = 1.237/ r class . the current accuracy does not include variations in r class resistance. the total classi? cation current for a pd also includes the ic quiescent current (i vportn_class ). see applications information. note 10: for the dhc package, this parameter is assured by design and wafer level testing. note 11: to disable the 25k signature, tie sigdisa to v portp or hold sigdisa high with respect to v portn . see applications information. note 12: the switching regulator is tested in a feedback loop that servos v fb to the output of the error ampli? er while maintaining i th /run at the midpoint of the current limit range. note 13: i pout_leak includes current drawn through p out by the power good status circuit. this current is compensated for in the 25k signature resistance and does not affect pd operation. note 14: the ltc4267 pd interface includes thermal protection. in the event of an overtemperature condition, the pd interface will turn off the switching regulator until the part cools below the overtemperature limit. the ltc4267 is also protected against thermal damage from incorrect classi? cation probing by the pse. if the ltc4267 exceeds the overtemperature threshold, the classi? cation load current is disabled. note 15: the pd interface includes dual level input current limit. at turn- on, before the p out load capacitor is charged, the pd current level is set to a low level. after the load capacitor is charged and the p out C v portn voltage difference is below the power good threshold, the pd switches to high level current limit. the pd stays in high level current limit until the input voltage drops below the uvlo turn-off threshold. note 16: peak current sense voltage is reduced dependent on duty cycle and an optional external resistor in series with the sense pin (r sl ). for details, refer to the programmable slope compensation feature in the applications information section. note 17: guaranteed by design. note 18: the pd interface includes overtemperature protection that is intended to protect the device from momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. electrical characteristics
ltc4267 5 4267fc input current vs input voltage 25k detection range input current vs input voltage input current vs input voltage input current vs input voltage signature resistance vs input voltage normalized uvlo threshold vs temperature power good output low voltage vs current p out leakage current current limit vs input voltage typical perfor uw ce characteristics a v portn voltage (v) 0 0 input current (ma) 0.1 0.2 0.3 0.4 0.5 ?2 ?4 ?6 ?8 4267 g01 ?10 t a = 25c v portn voltage (v) ?12 9.0 input current (ma) 9.5 10.5 11.0 11.5 ?14 ?16 4267 g03 10.0 ?18 ?20 ?22 12.0 85c ?40c class 1 operation v portn voltage (v) 0 0 input current (ma) 10 20 30 40 50 ?10 ?20 ?30 ?40 4267 g02 ?50 ?60 class 4 class 3 class 2 class 1 class 0 t a = 25c v portn voltage (v) 0 input current (ma) 1 2 3 ?45 ?55 4267 g04 ?60 ?40 ?50 excludes any load current t a = 25c v portn voltage (v) ?1 22 v1: v2: signature resistance (k ) 23 25 26 27 ?3 ?5 4267 g05 24 ?7 ?9 ?6 ?10 ?2 ?4 ?8 28 resistance = diodes: s1b t a = 25c = v i v2 ? v1 i 2 ? i 1 ieee upper limit ieee lower limit ltc4267 + 2 diodes ltc4267 only current (ma) 0 v pg_out (v) 2 3 8 4267 g07 1 0 2 4 6 10 4 t a = 25c p out pin voltage (v) 0 0 v out current (a) 30 60 120 90 20 40 4267 g08 60 v in = 0v t a = 25c v portn voltage (v) ?40 current limit (ma) 200 ?60 4267 g09 100 ?45 ?50 ?55 400 300 85c 85c ? 40c ? 40c high current mode low current mode temperature (c) ?40 ?2 normalized uvlo threshold (%) ?1 0 1 2 ?20 0 20 40 4267 g06 60 80 applicable to turn-on and turn-0ff thresholds
ltc4267 6 4267fc reference voltage vs temperature reference voltage vs supply voltage oscillator frequency vs temperature oscillator frequency vs supply voltage p vcc undervoltage lockout thresholds vs temperature p vcc shunt regulator voltage vs temperature i pvcc supply current vs temperature typical perfor a ce characteristics uw p vcc supply voltage (v) 6 799.0 v fb voltage (mv) 799.2 799.6 799.8 800.0 801.0 800.4 7 8 8.5 4267 g11 799.4 800.6 800.8 800.2 6.5 7.5 9 9.5 t a = 25c p vcc v clamp1ma temperature (c) ?50 oscillator frequency (khz) ?10 30 70 110 4267 g13 ?30 10 50 90 p vcc = 8v (with respect to pgnd) 240 230 220 210 200 190 180 p vcc supply voltage (v) 6 190 oscillator frequency (khz) 194 198 202 6.5 7 7.5 8 4267 g14 8.5 206 210 192 196 200 204 208 9 t a = 25c temperature (c) ?50 5.0 p vcc undervoltage lockout (v) 5.5 6.5 7.0 7.5 10.0 8.5 ?10 30 50 4267 g16 6.0 9.0 9.5 8.0 ?30 10 80 90 110 v turnon v turnoff temperature (c) ?50 9.0 p vcc (v) 9.1 9.3 9.4 9.5 10.0 9.7 ?10 30 50 4267 g17 9.2 9.8 9.9 9.6 ?30 10 70 90 110 i pvcc = 1ma temperature (c) ?50 215 supply current (a) 220 230 235 240 265 250 ?10 30 50 4267 g18 225 255 260 245 ?30 10 70 90 110 p vcc = 8v v ith/run = 1.3v temperature (c) ?50 v fb voltage (mv) 70 90 4267 g10 ?10 10 ?30 30 50 110 812 808 804 800 796 792 788 p vcc = 8v
ltc4267 7 4267fc peak current sense voltage vs temperature soft-start time vs temperature start-up i pvcc supply current vs temperature i th /run shutdown threshold vs temperature i th /run start-up current source vs temperature temperature (c) ?50 0 start-up supply current (a) 10 20 30 40 ?10 30 70 110 4267 g19 50 60 ?30 10 50 90 p vcc = v turnon ? 0.1v temperature (c) ?50 shutdown threshold (mv) 300 350 400 70 90 4267 g20 250 200 ?10 10 ?30 30 50 110 150 100 450 temperature (c) ?50 0 i th /run pin current source (na) 100 200 300 400 ?10 30 70 110 4267 g21 500 600 ?30 10 50 90 p vcc = v turnon + 0.1v v ith/run = 0v temperature (c) ?50 sense pin voltage (mv) 100 110 110 4267 g22 90 80 ?10 30 70 ?30 10 50 90 120 95 105 85 115 p vcc = 8v temperature (c) ?50 soft-start time (ms) 2.0 3.0 110 4267 g23 1.0 0 ?10 30 70 ?30 10 50 90 4.0 1.5 2.5 0.5 3.5 typical perfor a ce characteristics uw
ltc4267 8 4267fc i th /run (pin 2/pin 1): current threshold/run input. this pin performs two functions. it serves as the switching regulator error ampli? er compensation point as well as the run/shutdown control input. nominal voltage range is 0.7v to 1.9v. forcing the pin below 0.28v with respect to pgnd causes the controller to shut down. pgnd (pin 1, 8, 9, 16/pin 2, 15): switching regulator negative supply. this pin is the negative supply rail for the switching regulator controller and must be tied to p out . ngate (pin 3/pin 3): gate driver output. this pin drives the regulators external n-channel mosfet and swings from pgnd to p vcc . p vcc (pin 4/pin 4): switching regulator positive supply. this pin is the positive supply rail for the switching regula- tor and must be closely decoupled to pgnd. r class (pin 5/pin 5): class select input. used to set the cur- rent value the pd maintains during classi? cation. connect a resistor between r class and v portn (see table 2). v portn (pin 7/pin 7): negative power input. tie to the C48v input port through the input diodes. p out (pin 10/pin 10): power output. supplies C 48v to the switching regulator pgnd pin and any additional pd loads through an internal power mosfet that limits input current. p out is high impedance until the voltage reaches the turn-on uvlo threshold. the output is then current limited. see the application information section. ? p ? w ? r ? g ? d (pin 11/pin 11): power good output, open-drain. indicates that the pd mosfet is on and the switching regulator can start operation. low impedance indicates power is good. ? p ? w ? r ? g ? d is high impedance during detec- tion, classi? cation and in the event of a thermal overload. ? p ? w ? r ? g ? d is referenced to v portn . sigdisa (pin 12/pin 12): signature disable input. sigdisa allows the pd to present an invalid signature resistance and remain inactive. connecting sigdisa to v portp lowers the signature resistance to an invalid value and disables all functions of the ltc4267. if unused, tie sigdisa to v portn . v portp (pin 13/pin 13): positive power input. tie to the input port power return through the input diodes. sense (pin 14/pin 14): current sense. this pin performs two functions. it monitors the regulator switch current by reading the voltage across an external sense resistor. it also injects a current ramp that develops a slope compensation voltage across an optional external programming resistor. see the applications information section. v fb (pin 15/pin 16): feedback input. receives the feed- back voltage from the external resistor divider across the output. nc (pin 6/pin 6, 8, 9): no internal connection. backside connection (dhc only, pin 17): exposed pad. this exposed pad must be soldered to an electrically isolated and thermally conductive pc board heat sink. (gn/dhc) uu u pi fu ctio s
ltc4267 9 4267fc block diagram 4267 bd v portn bold line indicates high current path p out ? + pgnd r class pwrgd control circuits input current limit power good classification current load 1.237v en 375ma 140ma 9k 16k ? + en 25k signature resistor v portp sigdisa ? + ? + slope comp current ramp p vcc gate driver ngate sense 200khz oscillator undervoltage lockout q r current comparator shutdown comparator shutdown s 20mv i th /run error amplifier v fb soft- start clamp v cc shunt regulator switching logic and blanking circuit 0.28v p vcc < v turnon 0.3a p vcc ? + 1.2v 800mv reference overview the ltc4267 is partitioned into two major blocks: a powered device (pd) interface controller and a current mode ? yback switching regulator. the powered device (pd) interface is intended for use as the front end of a pd adhering to the ieee 802.3af standard, and includes a trimmed 25k signature resistor, classi? cation current source, and an input current limit circuit. with these functions integrated into the ltc4267, the signature and power interface for a pd can be built that meets all the requirements of the ieee 802.3af speci? cation with a minimum of external components. the switching regulator portion of the ltc4267 is a con- stant frequency current mode controller that is optimized for power over ethernet applications. the regulator is designed to drive a 6v n-channel mosfet and features soft-start and programmable slope compensation. the integrated error ampli? er and precision reference give the pd designer the option of using a nonisolated topology without the need for an external ampli? er or reference. the ltc4267 has been speci? cally designed to interface with both ieee compliant power sourcing equipment (pse) and legacy pses which do not meet the inrush current requirement of the ieee 802.3af speci? cation. by setting the initial inrush current limit to a low level, a pd using the ltc4267 minimizes the current drawn from the pse during start-up. after powering up, the ltc4267 switches to the high level current limit, thereby allowing the pd to consume up to 12.95w if an ieee 802.3af pse is present. this low level current limit also allows the ltc4267 to charge arbitrarily large load capacitors without exceeding the inrush limits of the ieee 802.3af speci? cation. this dual level current limit provides the system designer with ? exibility to design pds which are compatible with legacy pses while also being able to take advantage of the higher power available in an ieee 802.3af system. using an ltc4267 for the power and signature interface functions of a pd provides several advantages. the ltc4267 current limit circuit includes an onboard 100v, 400ma power mosfet. this low leakage mosfet is applicatio s i for atio wu uu
ltc4267 10 4267fc speci? ed to avoid corrupting the 25k signature resistor while also saving board space and cost. in addition, the in- rush current limit requirement of the ieee 802.3af standard can cause large transient power dissipation in the pd. the ltc4267 is designed to allow multiple turn-on sequences without overheating the miniature 16-lead package. in the event of excessive power cycling, the ltc4267 provides thermal overload protection to keep the onboard power mosfet within its safe operating area. operation the ltc4267 pd interface has several modes of opera- tion depending on the applied input voltage as shown in figure 1 and summarized in table 1. these modes satisfy the requirements de? ned in the ieee 802.3af speci? cation. the input voltage is applied to the v portn pin and must be negative relative to the v portp pin. voltages in the data sheet for the pd interface portion of the ltc4267 are with respect to v portp while the voltages for the switching regulator are referenced to pgnd. it is assumed that pgnd is tied to p out . note the use of different ground symbols throughout the data sheet. table 1. ltc4267 operational mode as a function of input voltage input voltage (v portn with respect to v portp ) ltc4267 mode of operation 0v to C 1.4v inactive C1.5v to C9.5v** 25k signature resistor detection C9.8v to C12.4v classi? cation load current ramps up from 0% to 100% C12.5v to uvlo* classi? cation load current active uvlo* to C57v power applied to switching regulator *v portn uvlo includes hysteresis. rising input threshold ? C 36.0v falling input threshold ? C30.5v **measured at ltc4267 pin. the ltc4267 meets the ieee 802.3af 10v minimum when operating with the required diode bridges. applicatio s i for atio wu uu figure 1. output voltage, ? p ? w ? r ? g ? d and pd current as a function of input voltage detection v1 classification uvlo turn-on uvlo off power bad uvlo off uvlo on uvlo turn-off = r load c1 pwrgd tracks v portn detection v2 ?10 time ?20 ?30 v portn (v) ?40 ?50 ?10 time ?20 ?30 p out (v) ?40 ?50 ?10 time ?20 ?30 pwrgd (v) ?40 ?50 i class pd current i lim_lo dv dt i lim_lo c1 = power bad power good detection i 1 classification i class detection i 2 load, i load (up to i lim_hi ) current limit, i lim_lo 4267 f01 i class dependent on r class selection i lim_lo = 140ma (nominal), i lim_hi = 375ma (nominal) i 1 = v1 ? 2 diode drops 25k ? i load = (up to i lim_hi ) v out r load i 2 = v2 ? 2 diode drops 25k ? v portp pse i in ltc4267 r9 r class r load v out c1 r class pwrgd p out pgnd v portn v in time voltages with respect to v portp
ltc4267 11 4267fc series diodes the ieee 802.3af-de? ned operating modes for a pd refer- ence the input voltage at the rj45 connector on the pd. the pd must be able to accept power of either polarity at each of its inputs, so it is common to install diode bridges (figure 2). the ltc4267 takes this into account by compensating for these diode drops in the threshold points for each range of operation. a similar adjustment is made for the uvlo voltages. detection during detection, the pse will apply a voltage in the range of C 2.8v to C10v on the cable and look for a 25k signature resistor. this identi? es the device at the end of the cable as a pd. with the terminal voltage in this range, the ltc4267 connects an internal 25k resistor between the v portp and v portn pins. this precision, temperature compensated resistor presents the proper signature to alert the pse that a pd is present and desires power to be applied. the internal low-leakage uvlo switch prevents the switching regulator circuitry from affecting the detec- tion signature. the ltc4267 is designed to compensate for the voltage and resistance effects of the ieee required diode bridge. the signature range extends below the ieee range to ac- commodate the voltage drop of the two diodes. the ieee speci? cation requires the pse to use a v/ i measurement technique to keep the dc offset of these diodes from af- fecting the signature resistance measurement. however, the diode resistance appears in series with the signature resistor and must be included in the overall signature resistance of the pd. the ltc4267 compensates for the two series diodes in the signature path by offsetting the resistance so that a pd built using the ltc4267 will meet the ieee speci? cation. in some applications it is necessary to control whether or not the pd is detected. in this case, the 25k signature resistor can be enabled and disabled with the use of the sigdisa pin (figure 3). disabling the signature via the sigdisa pin will change the signature resistor to 9k (typical) which is an invalid signature per the ieee 802.3af speci? cation. this invalid signature is present for pd input voltages from C 2.8v to C 10v. if the input rises above C 10v, the signature resistor reverts to 25k to minimize power dissipation in the ltc4267. to disable the signature, tie sigdisa to v portp . alternately, the sigdisa pin can be driven high with respect to v portn . when sigdisa is high, all functions of the pd interface are disabled. applicatio s i for atio wu uu rx ? 6 rx + 3 tx ? 2 tx + rj45 t1 powered device (pd) interface as defined by ieee 802.3af 4267 f02 1 7 8 5 4 spare ? spare + to phy br2 br1 v portp 8 4 d3 ltc4267 v portn figure 2. ltc4267 pd front end using diode bridges on main and spare inputs
ltc4267 12 4267fc v portp v portn ltc4267 4267 f03 25k signature resistor signature disable sigdisa 9k 16k to pse figure 3. 25k signature resistor with disable classi? cation once the pse has detected a pd, the pse may option- ally classify the pd. classi? cation provides a method for more ef? cient allocation of power by allowing the pse to identify lower power pds and allocate less power for these devices. the ieee 802.3af speci? cation de? nes ? ve classes (table 2) with varying power levels. the designer selects the appropriate classi? cation based on the power consumption of the pd. for each class, there is an as- sociated load current that the pd asserts onto the line during classi? cation probing. the pse measures the pd load current to determine the proper classi? cation and pd power requirements. during classi? cation (figure 4), the pse presents a ? xed voltage between C 15.5v and C 20.5v to the pd. with the input voltage in this range, the ltc4267 asserts a load current from the v portp pin through the r class resistor. the magnitude of the load current is set by the r class resistor. the resistor values associated with each class are shown in table 2. note that the switching regulator will not interfere with the classi? cation measurement since the ltc4267 has not passed power to the regulator. table 2. summary of ieee 802.3af power classi? cations and ltc4267 r class resistor selection maximum nominal ltc4267 power levels classi? cation r class at input of pd load current resistor class usage (w) (ma) ( , 1%) 0 default 0.44 to 12.95 <5 open 1 optional 0.44 to 3.84 10.5 124 2 optional 3.84 to 6.49 18.5 68.1 3 optional 6.49 to 12.95 28 45.3 4 reserved reserved* 40 30.9 *class 4 is currently reserved and should not be used. the ieee 802.3af speci? cation limits the classi? cation time to 75ms because a signi? cant amount of power is dissipated in the pd. the ltc4267 is designed to handle the power dissipation for this time period. if the pse probing exceeds 75ms, the ltc4267 may overheat. in this situation, the thermal protection circuit will engage and disable the classi? cation current source in order to protect the part. the ltc4267 stays in classi? cation mode until the input voltage rises above the uvlo turn-on voltage. v portn undervoltage lockout the ieee speci? cation dictates a maximum turn-on voltage of 42v and a minimum turn-off voltage of 30v for the pd. in addition, the pd must maintain large on-off hysteresis to prevent resistive losses in the wiring between the pse and the pd from causing start-up oscillation. the ltc4267 incorporates an undervoltage lockout (uvlo) circuit that monitors the line voltage at v portn to determine when to apply power to the integrated switching regulator (figure 5). before the power is applied to the switching regulator, the p out pin is high impedance and sitting at the ground potential since there is no charge on capacitor c1. when the input voltage rises above the uvlo turn-on threshold, the ltc4267 removes the detection and clas- si? cation loads and turns on the internal power mosfet. c1 charges up under the ltc4267 current limit control and the p out pin transitions from 0v to v portn . this sequence is shown in figure 1. the ltc4267 includes a hysteretic uvlo circuit on v portn that keeps power applied to the load until the input voltage falls below the uvlo turn-off threshold. once the input voltage drops below C30v, the internal power mosfet is turned off and figure 4. ieee 802.3af classi? cation probing applicatio s i for atio wu uu v portp r class v portn ltc4267 constant load current internal to ltc4267 4267 f04 r class current path v pd pse pse current monitor pse probing voltage source ?15.5v to ?20.5v
ltc4267 13 4267fc figure 5. ltc4267 v portn undervoltage lockout the classi? cation current is reenabled. c1 will discharge through the pd circuitry and the p out pin will go to a high impedance state. limit because the load capacitor is charged with a current below the ieee inrush current limit speci? cation. as the ltc4267 switches from the low to high level current limit, the current will increase momentarily. this current spike is a result of the ltc4267 charging the last 1.5v at the high level current limit. when charging a 10f capaci- tor, the current spike is typically 100s wide and 125% of the nominal low level current limit. the ltc4267 stays in the high level current limit mode until the input voltage drops below the uvlo turn-off threshold. this dual level current limit provides the sys- tem designer with the ? exibility to design pds which are compatible with legacy pses while also being able to take advantage of the higher power allocation available in an ieee 802.3af system. during the current limited turn on, a large amount of power is dissipated in the power mosfet. the ltc4267 pd interface is designed to accept this thermal load and is thermally protected to avoid damage to the onboard power mosfet. note that in order to adhere to the ieee 802.3af standard, it is necessary for the pd designer to ensure the pd steady state power consumption falls within the limits shown in table 2. in addition, the steady state current must be less than i lim_hi . power good the ltc4267 pd interface includes a power good circuit (figure 6) that is used to indicate that load capacitor c1 is fully charged and that the switching regulator can start operation. the power good circuit monitors the voltage across the internal uvlo power mosfet and ? p ? w ? r ? g ? d is asserted when the voltage falls below 1.5v. the power good circuit includes hysteresis to allow the ltc4267 to operate near the current limit point without inadvertently disabling ? p ? w ? r ? g ? d. the mosfet voltage must increase to 3v before ? p ? w ? r ? g ? d is disabled. if a sudden increase in voltage appears on the input line, this voltage step will be transferred through capacitor c1 and appear across the power mosfet. the response of the ltc4267 will depend on the magnitude of the voltage step, the rise time of the step, the value of capacitor c1 and the switching regulator load. for fast rising inputs, applicatio s i for atio wu uu input current limit ieee 802.3af speci? es a maximum inrush current and also speci? es a minimum load capacitor between the v portp and p out pins. to control turn-on surge current in the system, the ltc4267 integrates a dual level current limit circuit with an onboard power mosfet and sense resis- tor to provide a complete inrush control circuit without additional external components. at turn-on, the ltc4267 will limit the input current to the low level, allowing the load capacitor to ramp up to the line voltage in a controlled manner. the ltc4267 has been speci? cally designed to interface with legacy pses which do not meet the inrush current requirement of the ieee 802.3af speci? cation. at turn-on the ltc4267 current limit is set to the lower level. after c1 is charged up and the p out C v portn voltage difference is below the power good threshold, the ltc4267 switches to the high level current limit. the dual level current limit allows legacy pses with limited current sourcing capability to power up the pd while also allowing the pd to draw full power from an ieee 802.3af pse. the dual level current limit also allows use of arbitrarily large load capacitors. the ieee 802.3af speci? cation mandates that at turn-on the pd not exceed the inrush current limit for more than 50ms. the ltc4267 is not restricted to the 50ms time c1 5f min v portn v portp p out pgnd ltc4267 4267 f05 to pse undervoltage lockout circuit current-limited turn on + input ltc4267 voltage power mosfet 0v to uvlo* off >uvlo* on *uvlo includes hysteresis rising input threshold ?36v falling input threshold ?30.5v
ltc4267 14 4267fc pwrgd c1 5f min v portn p out 1.125v 300k 300k r9 100k ltc4267 thermal shutdown uvlo 4267 f06 to pse + ? + + ? i th /run pgnd pgnd the ltc4267 will attempt to quickly charge capacitor c1 using an internal secondary current limit circuit. in this scenario, the pse current limit should provide the overall limit for the circuit. for slower rising inputs, the 375ma current limit in the ltc4267 will set the charge rate of the capacitor c1. in either case, the ? p ? w ? r ? g ? d signal may go inactive brie? y while the capacitor is charged up to the new line voltage. in the design of a pd, it is necessary to determine if a step in the input voltage will cause the ? p ? w ? r ? g ? d signal to go inactive and how to respond to this event. in some designs, it may be desirable to ? lter the ? p ? w ? r ? g ? d signal so that intermittent power bad conditions are ignored. figure 7 demonstrates a method to insert a lowpass ? lter on the power good interface. for pd designs that use a large load capacitor and also consume a lot of power, it is important to delay activation of the switching regulator with the ? p ? w ? r ? g ? d signal. if the regulator is not disabled during the current-limited turn-on sequence, the pd circuitry will rob current intended for charging up the load capacitor and create a slow rising input, possibly causing the ltc4267 to go into thermal shutdown. the ? p ? w ? r ? g ? d pin connects to an internal open drain, 100v transistor capable of sinking 1ma. low impedance to v portn indicates power is good. ? p ? w ? r ? g ? d is high imped- ance during signature and classi? cation probing and in the event of a thermal overload. during turn-off, ? p ? w ? r ? g ? d is deactivated when the input voltage drops below 30v. in addition, ? p ? w ? r ? g ? d may go active brie? y at turn-on for fast rising input waveforms. ? p ? w ? r ? g ? d is referenced to the v portn pin and when active, will be near the v portn po- tential. connect the ? p ? w ? r ? g ? d pin to the switching regulator circuitry as shown in figure 7. figure 6. ltc4267 power good applicatio s i for atio wu uu figure 7. power good interface examples pd interface thermal protection the ltc4267 pd interface includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operat- ing temperatures. several factors create the possibility of signi? cant power dissipation within the ltc4267. at turn-on, before the load capacitor has charged up, the instantaneous power dissipated by the ltc4267 can be as much as 10w. as the load capacitor charges up, the power dissipation in the ltc4267 will decrease until it reaches a steady-state value dependent on the dc load current. the size of the load capacitor determines how fast the power dissipation in the ltc4267 will subside. at room temperature, the ltc4267 can typically handle load capacitors as large as 800f without going into thermal shutdown. with large load capacitors, the ltc4267 die temperature will increase by as much as 50c during a single turn-on sequence. if for some reason power were removed from the part and then quickly reapplied so that the ltc4267 had to charge up the load capacitor again, the temperature rise would be excessive if safety precautions were not implemented. the ltc4267 pd interface protects itself from thermal damage by monitoring the die temperature. if the die 4267 f07 ltc4267 v portn p out pgnd v portp i th /run i th /run to pse ?48v + c1 5f 100v alternate active-high enable for p vcc pin see applications information section active-high enable for run pin with internal pull-up r18 10k r9 100k d6 mmbd4148 c15 0.047f q1 fmmt2222 ltc3803 gnd optional auxiliary switching regulator pwrgd pgnd ltc4267 v portn p out pgnd v portp p vcc to pse ?48v + c1 5f 100v r18 10k r9 100k d6 mmbd4148 c15 0.047f q1 fmmt2222 pwrgd pgnd r start c pvcc c17
ltc4267 15 4267fc temperature exceeds the overtemperature trip point, the current is reduced to zero and very little power is dissi- pated in the part until it cools below the overtemperature set point. once the ltc4267 has charged up the load capacitor and the pd is powered and running, there will be minor residual heating due to the dc load current of the pd ? owing through the internal mosfet. the dhc package offers superior thermal performance by including an exposed pad that is soldered to an electrically isolated heat sink on the printed circuit board. during classi? cation, excessive heating of the ltc4267 can occur if the pse violates the 75ms probing time limit. to protect the ltc4267, thermal overload circuitry will dis- able classi? cation current if the die temperature exceeds the overtemperature trip point. when the die cools down below the trip point, classi? cation current is reenabled. the pd is designed to operate at a high ambient tem- perature and with the maximum allowable supply (57v). however, there is a limit to the size of the load capacitor that can be charged up before the ltc4267 reaches the overtemperature trip point. hitting the overtemperature trip point intermittently does not harm the ltc4267, but it will delay the completion of capacitor charging. capacitors up to 200f can be charged without a problem over the full operating temperature range. switching regulator main control loop due to space limitations, the basics of current mode dc/dc conversion will not be discussed here. the reader is referred to the detail treatment in application note 19 or in texts such as abraham pressmans switching power supply design. in a power over ethernet system, the majority of ap- plications involve an isolated power supply design. this means that the output power supply does not have any dc electrical path to the pd interface or the switching regulator primary. the dc isolation is achieved typically through a transformer in the forward path and an op- toisolator in the feedback path or a third winding in the transformer. the typical application circuit shown on the front page of the datasheet represents an isolated design using an optoisolator. in applications where a nonisolated topology is desired, the ltc4267 features a feedback port and an internal error ampli? er that can be enabled for this speci? c application. in the typical application circuit (figure 11), the isolated topology employs an external resistive voltage divider to present a fraction of the output voltage to an external error ampli? er. the error ampli? er responds by pulling an analog current through the input led on an optoiso- lator. the collector of the optoisolator output presents a corresponding current into the i th /run pin via a series diode. this method generates a feedback voltage on the i th /run pin while maintaining isolation. the voltage on the i th /run pin controls the pulse-width modulator formed by the oscillator, current comparator, and rs latch. speci? cally, the voltage at the i th /run pin sets the current comparators trip threshold. the current comparator monitors the voltage across a sense resistor in series with the source terminal of the external n-chan- nel mosfet. the ltc4267 turns on the external power mosfet when the internal free-running 200khz oscillator sets the rs latch. it turns off the mosfet when the cur- rent comparator resets the latch or when 80% duty cycle is reached, whichever happens ? rst. in this way, the peak current levels through the ? yback transformers primary and secondary are controlled by the i th /run voltage. in applications where a nonisolated topology is desirable (figure 11), an external resistive voltage divider can present a fraction of the output voltage directly to the v fb pin of the ltc4267. the divider must be designed so when the output is at its desired voltage, the v fb pin voltage will equal the 800mv onboard internal reference. the internal error ampli? er responds by driving the i th /run pin. the ltc4267 switching regulator performs in a similar manner as described previously. regulator start-up/shutdown the ltc4267 switching regulator has two shutdown mechanisms to enable and disable operation: an un- dervoltage lockout on the p vcc supply pin and a forced shutdown whenever external circuitry drives the i th /run pin low. the ltc4267 switcher transitions into and out of shutdown according to the state diagram (figure 8). it is important not to confuse the undervoltage lockout of the pd interface at v portn with that of the switching regulator at p vcc . they are independent functions. applicatio s i for atio wu uu
ltc4267 16 4267fc the undervoltage lockout mechanism on p vcc prevents the ltc4267 switching regulator from trying to drive the external n-channel mosfet with insuf? cient gate-to- adjustable slope compensation the ltc4267 switching regulator injects a 5a peak cur- rent ramp out through its sense pin which can be used for slope compensation in designs that require it. this current ramp is approximately linear and begins at zero current at 6% duty cycle, reaching peak current at 80% duty cycle. programming the slope compensation via a series resistor is discussed in the external interface and component selection section. external interface and component selection input interface transformer nodes on an ethernet network commonly interface to the outside world via an isolation transformer (figure 9). for poe devices, the isolation transformer must include a center tap on the media (cable) side. proper termination is required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. transformer vendors such as bel fuse, coil- craft, pulse and tyco (table 3) can provide assistance with selection of an appropriate isolation transformer and proper termination methods. these vendors have transformers speci? cally designed for use in pd applications. table 3. power over ethernet transformer vendors vendor contact information bel fuse inc. 206 van vorst street jersey city, nj 07302 tel: 201-432-0463 fax: 201-432-9542 http://www.belfuse.com coilcraft, inc. 1102 silver lake road cary, il 60013 tel: 847-639-6400 fax: 847-639-1469 http://www.coilcraft.com pulse engineering 12220 world trade drive san diego, ca 92128 tel: 858-674-8100 fax: 858-674-8262 http://www.pulseeng.com tyco electronics 308 constitution drive menlo park, ca 94025-1164 tel: 800-227-7040 fax: 650-361-2508 http://www.circuitprotection.com applicatio s i for atio wu uu figure 8. ltc4267 switching regulator start-up/shutdown state diagram source voltage. the voltage at the p vcc pin must exceed v turnon (nominally 8.7v with respect to pgnd) at least momentarily to enable operation. the p vcc voltage must fall to v turnoff (nominally 5.7v with respect to pgnd) before the undervoltage lockout disables the switching regulator. this wide uvlo hysteresis range supports applications where a bias winding on the ? yback trans- former is used to increase the ef? ciency of the ltc4267 switching regulator. the i th /run can be driven below v ithshdn (nominally 0.28v with respect to pgnd) to force the ltc4267 switching regulator into shutdown. an internal 0.3a current source always tries to pull the i th /run pin towards p vcc . when the i th /run pin voltage is allowed to exceed v ithshdn and p vcc exceeds v turnon , the ltc4267 switching regulator begins to operate and an internal clamp immediately pulls the i th /run pin to about 0.7v. in operation, the i th /run pin voltage will vary from roughly 0.7v to 1.9v to represent current comparator thresholds from zero to maximum. internal soft-start an internal soft-start feature is enabled whenever the ltc4267 switching regulator comes out of shutdown. speci? cally, the i th /run voltage is clamped and is prevented from reaching maximum until 1.4ms have passed. this allows the input current of the pd to rise in a smooth and controlled manner on start-up and stay within the current limit requirement of the ltc4267 interface. ltc4267 pwm shutdown ltc4267 pwm enabled v ith /run < v ithshdn (nominally 0.28v) v ith/run > v ithshdn and p vcc > v turnon (nominally 8.7v) p vcc < v turnoff 4267 f08 all voltages with respect to pgnd
ltc4267 17 4267fc diode bridge ieee 802.3af allows power wiring in either of two con? gu- rations: on the tx/rx wires or via the spare wire pairs in the rj45 connector. the pd is required to accept power in either polarity on either the main or spare inputs; therefore it is common to install diode bridges on both inputs in order to accommodate the different wiring con? gurations. figure 9 demonstrates an implementation of these diode bridges. the ieee 802.3af speci? cation also mandates that the leakage back through the unused bridge be less than 28a when the pd is powered with 57v. the ieee standard includes an ac impedance requirement in order to implement the ac disconnect function. capaci- tor c14 in figure 9 is used to meet this ac impedance requirement. a 0.1f capacitor is recommended for this application. the ltc4267 has several different modes of operation based on the voltage present between v portn and v portp pins. the forward voltage drop of the input diodes in a pd design subtracts from the input voltage and will affect the transition point between modes. when using the ltc4267, it is necessary to pay close attention to this forward voltage drop. selection of oversized diodes will help keep the pd thresholds from exceeding ieee speci? cations. the input diode bridge of a pd can consume over 4% of the available power in some applications. it may be desirable to use schottky diodes in order to reduce power loss. however, if the standard diode bridge is replaced with a schottky bridge, the transition points between the modes will be affected. figure 10 shows a technique for using schottky diodes while maintaining proper threshold points to meet ieee 802.3af compliance. d13 is added to compensate for the change in uvlo turn-on voltage caused by the schottky diodes and consumes little power. classi? cation resistor selection (r class ) the ieee speci? cation allows classifying pds into four distinct classes with class 4 being reserved for future use (table 2). an external resistor connected from r class to v portn (figure 4) sets the value of the load current. the designer should determine which power category the pd falls into and then select the appropriate value of r class from table 2. if a unique load current is required, the value of r class can be calculated as: r class = 1.237v/(i desired C i in_class ) where i in_class is the ltc4267 ic supply current during classi? cation and is given in the electrical speci? cations. the r class resistor must be 1% or better to avoid degrading the overall accuracy of the classi? cation circuit. resistor power dissipation will be 50mw maximum and is transient so heating is typically not a concern. in order to maintain loop stability, the layout should minimize capacitance at the r class node. the classi? cation circuit can be disabled by ? oating the r class pin. the r class pin should not be shorted to v portn as this would force the ltc4267 clas- si? cation circuit to attempt to source very large currents and quickly go into thermal shutdown. power good interface the ? p ? w ? r ? g ? d signal is controlled by a high voltage, open- drain transistor. the designer has the option of using this signal to enable the onboard switching regulator through the i th /run or the p vcc pins. examples of active-high interface circuits for controlling the switching regulator are shown in figure 7. in some applications, it is desirable to ignore intermittent power bad conditions. this can be accomplished by in- cluding capacitor c15 in figure 7 to form a lowpass ? lter. with the components shown, power bad conditions less than about 200s will be ignored. conversely, in other applications it may be desirable to delay assertion of ? p ? w ? r ? g ? d to the switching regulator using c pvcc or c17 as shown in figure 7. it is recommended that the designer use the power good signal to enable the switching regulator. using ? p ? w ? r ? g ? d ensures the capacitor c1 has reached within 1.5v of the ? nal value and is ready to accept a load. the ltc4267 is designed with wide power good hysteresis to handle sudden ? uctuations in the load voltage and current without prematurely shutting off the switching regulator. please refer to the power-up sequencing of the application information section. applicatio s i for atio wu uu
ltc4267 18 4267fc applicatio s i for atio wu uu figure 9. pd front end with isolation transformer, diode bridges and capacitor 16 14 15 1 3 2 rx ? 6 rx + 3 tx ? 2 tx + rj45 t1 pulse h2019 4267 f09 1 7 8 5 4 11 9 10 6 8 7 d3 smaj58a tvs br1 hd01 br2 hd01 to phy ltc4267 v portn spare ? spare + c14 0.1f 100v v portp 1 3 2 rx ? spare ? 6 rx + 3 tx ? 2 tx + j2 in from pse t1 rj45 1 7 8 5 4 6 8 7 txout + out to phy txout ? spare + rxout + rxout ? 16 14 15 11 9 10 notes: unless otherwise specified 1. all resistors are 5% 2. select r class for class 1-4 operation. refer to data sheet applications information section c2: avx 1808gc102mat d9 to d12, d14 to d17: diodes inc., b1100 t1: pulse h2019 r class 1% r class v portn d13 mmsd4148 c11 0.1f 100v d6 smaj58a r30 75 ? c24 0.01f 200v r31 75 ? c25 0.01f 200v r1 75 ? c7 0.01f 200v r2 75 ? c3 0.01f 200v c2 1000pf 2kv d10 b1100 d12 b1100 d9 b1100 d11 b1100 d17 b1100 d16 b1100 d15 b1100 d14 b1100 v portp ltc4267 4267 f10 figure 10. pd front end with isolation transformer, 2nd schottky diode bridge
ltc4267 19 4267fc applicatio s i for atio wu uu signature disable interface to disable the 25k signature resistor, connect sigdisa pin to the v portp pin. alternately, sigdisa pin can be driven high with respect to v portn . an example of a signature disable interface is shown in figure 16, option 2. note that the sigdisa input resistance is relatively large and the threshold voltage is fairly low. because of high voltages present on the printed circuit board, leakage currents from the v portp pin could inadvertently pull sigdisa high. to ensure trouble-free operation, use high voltage layout techniques in the vicinity of sigdisa. if unused, connect sigdisa to v portn . load capacitor the ieee 802.3af speci? cation requires that the pd maintain a minimum load capacitance of 5f (provided by c1 in figure 11). it is permissible to have a much larger load capacitor and the ltc4267 can charge very large load capacitors before thermal issues become a problem. the load capacitor must be large enough to provide suf? cient energy for proper operation of the switching regulator. however, the capacitor must not be too large or the pd design may violate ieee 802.3af requirements. if the load capacitor is too large, there can be a problem with inadvertent power shutdown by the pse. consider the following scenario. if the pse is running at C 57v (maximum allowed) and the pd has detected and powered up, the load capacitor will be charged to nearly C 57v. if for some reason the pse voltage is suddenly reduced to C 44v (minimum allowed), the input bridge will reverse bias and the pd power will be supplied by the load capacitor. depending on the size of the load capacitor and the dc load of the pd, the pd will not draw any power for a period of time. if this period of time exceeds the ieee 802.3af 300ms disconnect delay, the pse will remove power from the pd. for this reason, it is necessary to ensure that inadvertent shutdown cannot occur. very small output capacitors (10f) will charge very quickly in current limit. the rapidly changing voltage at the output may reduce the current limit temporarily, caus- ing the capacitor to charge at a somewhat reduced rate. conversely, charging a very large capacitor may cause the current limit to increase slightly. in either case, once the output voltage reaches its ? nal value, the input current limit will be restored to its nominal value. the load capacitor can store signi? cant energy when fully charged. the design of a pd must ensure that this energy is not inadvertently dissipated in the ltc4267. the polar- ity-protection diode(s) prevent an accidental short on the cable from causing damage. however, if the v portn pin is shorted to v portp inside the pd while the capacitor is charged, current will ? ow through the parasitic body diode of the internal mosfet and may cause permanent damage to the ltc4267. maintain power signature in an ieee 802.3af system, the pse uses the maintain power signature (mps) to determine if a pd continues to require power. the mps requires the pd to periodically draw at least 10ma and also have an ac impedance less than 26.25k in parallel with 0.05f. if either the dc current is less than 10ma or the ac impedance is above 26.25k , the pse may disconnect power. the dc current must be less than 5ma and the ac impedance must be above 2m to guarantee power will be removed. selecting feedback resistor values the regulated output voltage of the switching regulator is determined by the resistor divider across v out (r1 and r2 in figure 11) and the error ampli? er reference voltage v ref . the ratio of r2 to r1 needed to produce the desired voltage can be calculated as: r2 = r1 ? (v out C v ref )/v ref in an isolated power supply application, v ref is determined by the designers choice of an external error ampli? er. commercially available error ampli? ers or programmable shunt regulators may include an internal reference of 1.25v or 2.5v. since the ltc4267 internal reference and error ampli? er are not used in an isolated design, tie the v fb pin to pgnd. in a nonisolated power supply application, the ltc4267 onboard internal reference and error ampli? er can be used. the resistor divider output can be tied directly to the v fb pin. the internal reference of the ltc4267 is 0.8v nominal.
ltc4267 20 4267fc choose resistance values for r1 and r2 to be as large as possible to minimize any ef? ciency loss due to the static current drawn from v out , but just small enough so that when v out is in regulation, the error caused by the nonzero input current from the output of the resistor divider to the error ampli? er pin is less than 1%. error ampli? er and optoisolator considerations in an isolated topology, the selection of the external error ampli? er depends on the output voltage of the switching regulator. typical error ampli? ers include a voltage refer- ence of either 1.25v or 2.5v. the output of the ampli? er and the ampli? er upper supply rail are often tied together internally. the supply rail is usually speci? ed with a wide upper voltage range, but it is not allowed to fall below the reference voltage. this can be a problem in an isolated switcher design if the ampli? er supply voltage is not prop- erly managed. when the switcher load current decreases and the output voltage rises, the error ampli? er responds by pulling more current through the led. the led voltage can be as large as 1.5v, and along with r lim , reduces the supply voltage to the error ampli? er. if the error amp does not have enough headroom, the voltage drop across the led and r lim may shut the ampli? er off momentarily, causing a lock-up condition in the main loop. the switcher will undershoot and not recover until the error ampli? er releases its sink current. care must be taken to select the reference voltage and r lim value so that the error ampli? er always has enough headroom. an alternate solution that avoids these problems is to utilize the lt1431 or lt4430 where the output of the error ampli? er and ampli? er supply rail are brought out to separate pins. the pd designer must also select an optoisolator such that its bandwidth is suf? ciently wider than the bandwidth of the main control loop. if this step is overlooked, the main control loop may be dif? cult to stabilize. the output collector resistor of the optoisolator can be selected for an increase in bandwidth at the cost of a reduction in gain of this stage. output transformer design considerations since the external feedback resistor divider sets the output voltage, the pd designer has relative freedom in selecting the transformer turns ratio. the pd designer can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2) which yields more freedom in setting the total turns and mutual inductance and may allow the use of an off the shelf transformer. transformer leakage inductance on either the primary or secondary causes a voltage spike to occur after the output switch (q1 in figure 11) turns off. the input supply volt- age plus the secondary-to-primary referred voltage of the ? yback pulse (including leakage spike) must not exceed the allowed external mosfet breakdown rating. this spike is increasingly prominent at higher load currents, where more stored energy must be dissipated. in some cases, a snubber circuit will be required to avoid overvoltage breakdown at the mosfets drain node. application note 19 is a good reference for snubber design. current sense resistor consideration the external current sense resistor (r sense in figure 11) allows the designer to optimize the current limit behavior for a particular application. as the current sense resistor is varied from several ohms down to tens of milliohms, peak swing current goes from a fraction of an ampere to several amperes. care must be taken to ensure proper circuit operation, especially for small current sense resis- tor values. choose r sense such that the switching current exercises the entire range of the i th /run voltage. the nominal voltage range is 0.7v to 1.9v and r sense can be determined by experiment. the main loop can be temporarily stabilized by connecting a large capacitor on the power supply. apply the maximum load current allowable at the power sup- ply output based on the class of the pd. choose r sense such that i th /run approaches 1.9v. finally, exercise the output load current over the entire operating range and ensure that i th /run voltage remains within the 0.7v to 1.9v range. layout is critical around the r sense resistor. for example, a 0.020 sense resistor, with one milliohm (0.001 ) of parasitic resistance will cause a 5% reduction in peak switch current. the resistance of printed circuit copper traces cannot necessarily be ignored and good layout techniques are mandatory. applicatio s i for atio wu uu
ltc4267 21 4267fc applicatio s i for atio wu uu figure 11. typical ltc4267 application circuits p vcc p vcc p vcc v portp r class sigdisa v portn i th /run ltc4267 ngate sense v fb r3 d1 d2 c out pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd p out c1 l sec l pri l bias c pvcc c c v out 4267 f11 r sense r sl r start r2 r1 q1 t1 r class p vcc v portp r class sigdisa v portn i th /run ltc4267 ngate sense v fb d1 c out 0.1f 100v 0.1f 100v pgnd pgnd pgnd pgnd p out c1 l sec l pri c pvcc v out r sense r sl r start q1 r2 r1 r lim ?48v from data pair ?48v from spare pair r class v portp v portp v portn t1 c iso optoisolator c c r c error amplifier isolated design example nonisolated design example + ? + ? ?48v from data pair ?48v from spare pair + ? + ?
ltc4267 22 4267fc applicatio s i for atio wu uu programmable slope compensation the ltc4267 switching regulator injects a ramping current through its sense pin into an external slope compensation resistor (r sl in figure 11). this current ramp starts at zero after the ngate pin has been high for the ltc4267s minimum duty cycle of 6%. the current rises linearly to- wards a peak of 5a at the maximum duty cycle of 80%, shutting off once the ngate pin goes low. a series resis- tor (r sl ) connecting the sense pin to the current sense resistor (r sense ) develops a ramping voltage drop. from the perspective of the ltc4267 sense pin, this ramping voltage adds to the voltage across the sense resistor, effectively reducing the current comparator threshold in proportion to duty cycle. this stabilizes the control loop against subharmonic oscillation. the amount of reduction in the current comparator threshold (?v sense ) can be calculated using the following equation: ?v sense = 5a ? r sl ? [(duty cycle C 6%)/74%] note: the ltc4267 enforces 6% < duty cycle < 80%. designs not needing slope compensation may replace r sl with a short-circuit. applications employing a third transformer winding a standard operating topology may employ a third winding on the transformers primary side that provides power to the ltc4267 switching regulator via its p vcc pin (figure 11). however, this arrangement is not inherently self-starting. start-up is usually implemented by the use of an external trickle-charge resistor (r start ) in conjunc- tion with the internal wide hysteresis undervoltage lockout circuit that monitors the p vcc pin voltage. r start is connected to v portp and supplies a current, typically 100a, to charge c pvcc . after some time, the voltage on c pvcc reaches the p vcc turn-on threshold. the ltc4267 switching regulator then turns on abruptly and draws its normal supply current. the ngate pin begins switching and the external mosfet (q1) begins to deliver power. the voltage on c pvcc begins to decline as the switching regulator draws its normal supply current, which exceeds the delivery from r start . after some time, typically tens of milliseconds, the output voltage approaches the desired value. by this time, the third transformer winding is providing virtually all the supply current required by the ltc4267 switching regulator. one potential design pitfall is under-sizing the value of capacitor c pvcc . in this case, the normal supply current drawn through p vcc will discharge c pvcc rapidly before the third winding drive becomes effective. depending on the particular situation, this may result in either several off-on cycles before proper operation is reached or permanent relaxation oscillation at the p vcc node. resistor r start should be selected to yield a worst-case minimum charging current greater that the maximum rated ltc4267 start-up current to ensure there is enough current to charge c pvcc to the p vcc turn-on threshold. r start should also be selected large enough to yield a worst-case maximum charging current less than the minimum-rated p vcc supply current, so that in operation, most of the p vcc current is delivered through the third winding. this results in the highest possible ef? ciency. capacitor c pvcc should then be made large enough to avoid the relaxation oscillation behavior described previously. this is dif? cult to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. empirical testing is recommended. the third transformer winding should be designed so that its output voltage, after accounting for the forward diode voltage drop, exceeds the maximum p vcc turn-off threshold. also, the third windings nominal output voltage should be at least 0.5v below the minimum rated p vcc clamp voltage to avoid running up against the ltc4267 shunt regulator, needlessly wasting power. p vcc shunt regulator in applications including a third transformer winding, the internal p vcc shunt regulator serves to protect the ltc4267 switching regulator from overvoltage transients as the third winding is powering up. if a third transformer winding is undesirable or unavail- able, the shunt regulator allows the ltc4267 switching regulator to be powered through a single dropping resistor from v portp as shown in figure 12. this simplicity comes at the expense of reduced ef? ciency due to static power dissipation in the r start dropping resistor.
ltc4267 23 4267fc the shunt regulator can sink up to 5ma through the p vcc pin to pgnd. the values of r start and c pvcc must be selected for the application to withstand the worst-case load conditions and drop on p vcc , ensuring that the p vcc turn-off threshold is not reached. c pvcc should be sized suf? ciently to handle the switching current needed to drive ngate while maintaining minimum switching voltage. actual current needed to power the ltc4267 switching regulator goes through q1 and p vcc sources current on an as-needed basis. the static current is then limited only to the current through r b and d1. applicatio s i for atio wu uu figure 12. powering the ltc4267 switching regulator via the shunt regulator figure 13. powering the ltc4267 switching regulator with an external preregulator v portp p vcc pgnd p out v portn ltc4267 ?48 from pse r start c pvcc + ? pgnd 4267 f14 external preregulator the circuit in figure 13 shows a third way to power the ltc4267 switching regulator circuit. an external series preregulator consists of a series pass transistor q1, zener diode d1, and a bias resistor r b . the preregulator holds p vcc at 7.6v nominal, well above the maximum rated p vcc turn-off threshold of 6.8v. resistor r start momentarily charges the p vcc node up to the p vcc turn-on threshold, enabling the switching regulator. the voltage on c pvcc begins to decline as the switching regulator draws its normal supply current, which exceeds the delivery of r start . after some time, the output voltage approaches the desired value. by this time, the pass transistor q1 catches the declining voltage on the p vcc pin, and provides virtually all the supply current required by the ltc4267 switching regulator. c pvcc should be sized suf? ciently to handle the switching current needed to drive ngate while maintaining minimum switching voltage. the external preregulator has improved ef? ciency over the simple resistor-shunt regulator method mentioned previously. r b can be selected so that it provides a small current necessary to maintain the zener diode voltage and the maximum possible base current q1 will encounter. the v portp p vcc pgnd p out v portn ltc4267 ?48 from pse r start c pvcc + ? pgnd pgnd pgnd q1 d1 8.2v r b 4267 f15 compensating the main loop in an isolated topology, the compensation point is typically chosen by the components con? gured around the external error ampli? er. shown in figure 14, a series rc network is connected from the compare voltage of the error am- pli? er to the error ampli? er output. in pd designs where transient load response is not critical, replace r z with a short. the product of r2 and c c should be suf? ciently large to ensure stability. when fast settling transient response is critical, introduce a zero set by r z c c . the pd designer must ensure that the faster settling response of the output voltage does not compromise loop stability. in a nonisolated design, the ltc4267 incorporates an internal error ampli? er where the i th /run pin serves as a compensation point. in a similar manner, a series rc network can be connected from i th /run to pgnd as shown in figure 15. c c and r z are chosen for optimum load and line transient response. figure 14. main loop compensation for an isolated design r1 r2 c c r z to opto- isolator 4267 f14 v out
ltc4267 24 4267fc selecting the switching transistor with the n-channel power mosfet driving the primary of the transformer, the inductance will cause the drain of the mosfet to traverse twice the voltage across v portp and pgnd. the ltc4267 operates with a maximum supply of C 57v; thus the mosfet must be rated to handle 114v or more with suf? cient design margin. typical transistors have 150v ratings while some manufacturers have developed 120v rated mosfets speci? cally for power-over-ethernet applications. the ngate pin of the ltc4267 drives the gate of the n-channel mosfet. ngate will traverse a rail-to-rail volt- age from pgnd to p vcc . the designer must ensure the mosfet provides a low on resistance when switched to p vcc as well as ensure the gate of the mosfet can handle the p vcc supply voltage. for high ef? ciency applications, select an n-channel mosfet with low total gate charge. the lower total gate charge improves the ef? ciency of the ngate drive circuit and minimizes the switching current needed to charge and discharge the gate. auxiliary power source in some applications, it may be desirable to power the pd from an auxiliary power source such as a wall trans- former. the auxiliary power can be injected into the pd at several locations and various trade-offs exist. power can be injected at the 3.3v or 5v output of the isolated power supply with the use of a diode oring circuit. this method accesses the internal circuits of the pd after the isolation barrier and therefore meets the 802.3af isolation safety requirements for the wall transformer jack on the pd. power can also be injected into the pd interface portion of the ltc4267. in this case, it is necessary to ensure the user cannot access the terminals of the wall transformer jack on the pd since this would compromise the 802.3af isolation safety requirements. figure 16 demonstrates three methods of diode oring external power into a pd. option 1 inserts power before the ltc4267 interface controller while options 2 and 3 bypass the ltc4267 interface controller section and power the switching regulator directly. if power is inserted before the ltc4267 interface con- troller, it is necessary for the wall transformer to exceed the ltc4267 uvlo turn-on requirement and include a transient voltage suppressor (tvs) to limit the maximum voltage to 57v. this option provides input current limit for the transformer, provides a valid power good signal, and simpli? es power priority issues. as long as the wall transformer applies power to the pd before the pse, it will take priority and the pse will not power up the pd because the wall power will corrupt the 25k signature. if the pse is already powering the pd, the wall transformer power will be in parallel with the pse. in this case, prior- ity will be given to the higher supply voltage. if the wall transformer voltage is higher, the pse should remove the line voltage since no current will be drawn from the pse. on the other hand, if the wall transformer voltage is lower, the pse will continue to supply power to the pd and the wall transformer will not be used. proper operation should occur in either scenario. if auxiliary power is applied directly to the ltc4267 switch- ing regulator (bypassing the ltc4267 pd interface), a different set of tradeoffs arise. in the con? guration shown in option 2, the wall transformer does not need to exceed the ltc4267 turn-on uvlo requirement; however, it is necessary to include diode d9 to prevent the transformer from applying power to the ltc4267 interface controller. the transformer voltage requirement will be governed by the needs of the onboard switching regulator. however, power priority issues require more intervention. if the wall transformer voltage is below the pse voltage, then priority will be given to the pse power. the ltc4267 interface controller will draw power from the pse while the transformer will sit unused. this con? guration is not a problem in a poe system. on the other hand, if the wall applicatio s i for atio wu uu figure 15. main loop compensation for a nonisolated design ltc4267 c c r z i th /run pgnd 4267 f15
ltc4267 25 4267fc figure 16. auxiliary power source for pd applicatio s i for atio wu uu rx ? 6 rx + 3 tx ? 2 tx + rj45 t1 1 7 8 5 4 spare ? + ? spare + isolated wall transformer to phy v portp option 1: auxiliary power inserted before ltc4267 pd option 2: auxiliary power inserted after ltc4267 pd with signature disabled v portn p out pgnd pgnd 38v to 57v d8 s1b d3 smaj58a tvs c1 pgnd pgnd c14 0.1f 100v rx ? 6 rx + 3 tx ? 2 tx + rj45 t1 1 7 8 5 4 spare ? + ? spare + isolated wall transformer to phy v portp sigdisa ltc4267 ltc4267 br2 hd01 ~ ~ + ? br1 hd01 ~ ~ + ? br1 hd01 ~ ~ + ? v portn p out 4267 f16 d10 s1b d3 smaj58a tvs c1 100k d9 s1b option 3: auxiliary power applied to ltc4267 pd and switching regulator rx ? 6 rx + 3 tx ? 2 tx + rj45 t1 1 7 8 5 4 spare ? + ? spare + isolated wall transformer to phy 38v to 57v v portp ltc4267 v portn p out d10 s1b d3 smaj58a tvs c1 c14 0.1f 100v c14 0.1f 100v br2 hd01 ~ ~ + ? br1 hd01 ~ ~ + ? br2 hd01 ~ ~ + ? 100k bss63 r start c pvcc r start c pvcc r start c pvcc pgnd p vcc pgnd p vcc p vcc
ltc4267 26 4267fc transformer voltage is higher than the pse voltage, the ltc4267 switching regulator will draw power from the transformer. in this situation, it is necessary to address the issue of power cycling that may occur if a pse is present. the pse will detect the pd and apply power. if the switcher is being powered by the wall transformer, then the pd will not meet the minimum load requirement and the pse will subsequently remove power. the pse will again detect the pd and power cycling will start. with a transformer voltage above the pse voltage, it is necessary to either disable the signature, as shown in option 2, or install a minimum load on the output of the ltc4267 interface to prevent power cycling. the third option also applies power directly to the ltc4267 switching regulator, bypassing the ltc4267 interface controller and omitting diode d9. with the diode omit- ted, the transformer voltage is applied to the ltc4267 interface controller in addition to the switching regulator. for this reason, it is necessary to ensure that the trans- former maintain the voltage between 38v and 57v to keep the ltc4267 interface controller in its normal operating range. the third option has the advantage of automatically disabling the 25k signature resistor when the external voltage exceeds the pse voltage. power-up sequencing the ltc4267 the ltc4267 consists of two functional cells, the pd interface and the switching regulator, and the power up sequencing of these two cells must be carefully considered. the pd designer should ensure that the switching regulator does not begin operation until the interface has completed charging up the load capacitor. this will ensure that the switcher load current does not compete with the load capacitor charging current provided by the pd interface current limit circuit. overlooking this consideration may result in slow power supply ramp up, power-up oscillation, and possibly thermal shutdown. the ltc4267 includes a power good signal in the pd inter- face that can be used to indicate to the switching regulator that the load capacitor is fully charged and ready to handle the switcher load. figure 7 shows two examples of ways the ? p ? w ? r ? g ? d signal can be used to control the switching regulator. the ? rst example employs an n-channel mosfet to drive the i th /run port below the shutdown threshold (typically 0.28v). the second example drives p vcc below the p vcc turn-off threshold. employing the second example has the added advantage of adding delay to the switching regulator start-up beyond the time the power good signal becomes active. the second example ensures additional timing margin at start-up without the need for added delay components. in applications where it is not desirable to utilize the power good signal, suf? cient timing margin can be achieved with r start and c pvcc . r start and c pvcc should be set to a delay of two to three times longer than the duration needed to charge up c1. layout considerations for the ltc4267 the most critical layout considerations for the ltc4267 are the placement of the supporting external components associated with the switching regulator. ef? ciency, stability, and load transient response can deteriorate without good layout practices around critical components. for the ltc4267 switching regulator, the current loop through c1, t1 primary, q1, and r sense must be given careful layout attention. (refer to figure 11.) because of the high switching current circulating in this loop, these components should be placed in close proximity to each other. in addition, wide copper traces or copper planes should be used between these components. if vias are necessary to complete the connectivity of this loop, placing multiple vias lined perpendicular to the ? ow of current is essential for minimizing parasitic resistance and reducing current density. since the switching frequency and the power levels are substantial, shielding and high frequency layout techniques should be employed. a low current, low impedance alternate connection should be employed between the pgnd pins of the ltc4267 and the pgnd side of r sense , away from the high current loop. this kelvin sensing will ensure an accurate representation of the sense voltage is measured by the ltc4267. the placement of the feedback resistors r1 and r2 as well as the compensation capacitor c c is very important in the accuracy of the output voltage, the stability of the main control loop, and the load transient response. in an isolated design application, r1, r2, and c c should be placed as close as possible to the error ampli? ers input applicatio s i for atio wu uu
ltc4267 27 4267fc with minimum trace lengths and minimum capacitance. in a nonisolated application, r1, and r2 should be placed as close as possible to the v fb pin of the ltc4267 and c c should be placed close to the i th /run pin of the ltc4267. in essence, a tight overall layout of the high current loop and careful attention to current density will ensure suc- cessful operation of the ltc4267 in a pd. the pd interface section of the ltc4267 is relatively im- mune to layout problems. excessive parasitic capacitance on the r class pin should be avoided. if using the dhc package, include an electrically isolated heat sink to which the exposed pad on the bottom of the package can be soldered. for optimum thermal performance, make the heat sink as large as possible. the sigdisa pin is adjacent to the v portp pin and any coupling, whether resistive applicatio s i for atio wu uu or capacitive may inadvertently disable the signature resistance. to ensure consistent behavior, the sigdisa pin should be electrically connected and not left ? oating. voltages in a pd can be as large as C 57v, so high voltage layout techniques should be employed. electro static discharge and surge protection the ltc4267 is speci? ed to operate with an absolute maximum voltage of C100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world (primarily v portn and v portp ) can routinely see peak voltages in excess of 10kv. to protect the ltc4267, it is highly recommended that a transient voltage suppressor be installed between the diode bridge and the ltc4267 (d3 in figure 2).
ltc4267 28 4267fc typical applicatio s u class 3 pd with 5v nonisolated power supply p vcc ngate pwrgd sense v fb i th /run v portp r class sigdisa v portn ltc4267 45.3 ? 1% 100k 1f 300f** coiltronics ctx-02-15242 bas516 ups840 smaj58a 5v 1.8a hd01 hd01 + ? + ? ?48v from data pair ?48v from spare pair 4267 ta03 fdc2512 0.04 ? 1% 10k 220k 220 ? 42.2k 1% 27k 150pf 200v 9.1v 22nf 0.1f 5f* min pgnd p out mmbta42 8.06k 1% *1f ceramic + 4.7f tantalum ** three 100f ceramics
ltc4267 29 4267fc typical applicatio s u class 3 pd with triple output isolated power supply p vcc ngate pwrgd i th /run v fb v portp sigdisa v portn ltc4267 45.3 ? j1 smaj58a p vcc 6.8 k 0.1f 5f*** min p out pgnd 0.1f 6.8nf 2.2nf 250vac ps2911 4267 ta04 j1 halo hfj11 rp28e-l12 integrated jack t1 coilcraft d1766-al t2 pulse pa0184 * two 100 f capacitors in parallel ** 47 f and 220 f in parallel *** 1 f ceramic + 4.7 f tantalum bas516 220k 4.7f p vcc 220k 8.2v 8.2k bcx5616 mmbt3904 51 ? 10p bas516 0.068 1% 10k 0.47 f 20 ? 0.033 f 4.7 f 267 f** 200 f* 100 f 49.9k 1% 49.9k 1% 3.3v at 0.5a 2.5v at 1.5a 1.8v at 2.5a chassis t1 t2 ph7030dl ph7030dl ph7030dl bat54slt1 1k zrl431 10 ? 2.2k si3440dv si3442dv r class sense 14 13 12 11 10 9 8 7 6 5 4 3 2 1 to phy to phy
ltc4267 30 4267fc u package descriptio dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 1 8 16 9 (dhc16) dfn 1103 recommended solder pad pitch and dimensions
ltc4267 31 4267fc package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 15 14 13 .189 ? .196* (4.801 ? 4.978) 12 11 10 9 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .007 ? .0098 (0.178 ? 0.249) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc4267 32 4267fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0107 rev c ? printed in usa part number description comments ltc1737 high power isolated flyback controller sense output voltage directly from primary side winding ltc1871 wide input range, no r sense tm current mode adjustable switching frequency, programmable undervoltage lockout, flyback, boost and sepic controller optional burst mode ? operation at light load ltc3803 current mode flyback dc/dc controller in thinsot tm 200khz constant frequency, adjustable slope compensation, optimized for high input voltage applications ltc4257 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classi? cation ltc4257-1 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classi? cation, with dual current limit supports legacy applications ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only, ieee-compliant pd detection and classi? cation, autonomous operation or i 2 c tm control ltc4259a quad ieee 802.3af power over ethernet controller ac or dc disconnect ieee-compliant pd detection and classi? cation, autonomous operation or i 2 c tm control burst mode is a registered trademark of linear technology corporation. thinsot is a trademark of linear technology corporation. related parts high-ef? ciency class 3 pd with 3.3v isolated power supply p vcc ngate sense i th /run pwrgd v fb v portp r class sigdisa v portn ltc4267 45.3 ? 1% 220k 330 220k p vcc 4.7f smaj58a mmsd4148 pulse pa1136 mmsd4148 bas516 bas516 mmtba42 ?48v from data pair ?48v from spare pair si3440 2n7002 p vcc 100 k p vcc 6.8 k 10 k 10 k 0.1f 5f* min b1100 (8 places) p out pgnd 9.1v 150pf 510 500 ? 0.068 ? 1% 100k 1% 60.4k 1% 570f** 33nf 10 ? 470pf 2200pf ?y? cap 250vac ps2911 tlv431 sbm1040 3.3v 2.6a chassis 4267 ta02 *1f ceramic + 4.7f tantalum **100f ceramic + 470f tantalum bas516 typical application

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